Fault Covering Problems in Reconfigurable VLSI Systems

Fault Covering Problems in Reconfigurable VLSI Systems

Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems.

Author: Ran Libeskind-Hadas

Publisher: Springer Science & Business Media

ISBN: 9781461536147

Category: Technology & Engineering

Page: 130

View: 425

Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.
Categories: Technology & Engineering

Fault Covering Problems in Reconfigurable VLSI Systems

Fault Covering Problems in Reconfigurable VLSI Systems

Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems.

Author: Ran Libeskind-Hadas

Publisher: Springer

ISBN: 1461366062

Category: Technology & Engineering

Page: 130

View: 564

Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.
Categories: Technology & Engineering

Defect and Fault Tolerance in VLSI Systems

Defect and Fault Tolerance in VLSI Systems

AN INTEGER LINEAR PROGRAMMING APPROACH TO GENERAL FAULT COVERING PROBLEMS N. Hasan, J. Cong, and C.L. Liu ... One way to increase the yield in chip production is to use reconfigurable chips in which there are redundant elements that can ...

Author: C.H. Stapper

Publisher: Springer Science & Business Media

ISBN: 9781475799576

Category: Technology & Engineering

Page: 316

View: 770

Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.
Categories: Technology & Engineering

Defect and Fault Tolerance in VLSI Systems

Defect and Fault Tolerance in VLSI Systems

The five papers in Chapter 9 discuss reconfigurable VLSI arrays. ... The last paper, by N. Hasan, J. Cong, and C.L. Liu, introduces a general model for fault-covering problems in reconfigurable arrays representing the relationship ...

Author: Israel Koren

Publisher: Springer Science & Business Media

ISBN: 9781461567998

Category: Computers

Page: 362

View: 657

This book contains an edited selection of papers presented at the International Workshop on Defect and Fault Tolerance in VLSI Systems held October 6-7, 1988 in Springfield, Massachusetts. Our thanks go to all the contributors and especially the members of the program committee for the difficult and time-consuming work involved in selecting the papers that were presented in the workshop and reviewing the papers included in this book. Thanks are also due to the IEEE Computer Society (in particular, the Technical Committee on Fault-Tolerant Computing and the Technical Committee on VLSI) and the University of Massachusetts at Amherst for sponsoring the workshop, and to the National Science Foundation for supporting (under grant number MIP-8803418) the keynote address and the distribution of this book to all workshop attendees. The objective of the workshop was to bring t. ogether researchers and practition ers from both industry and academia in the field of defect tolerance and yield en ha. ncement in VLSI to discuss their mutual interests in defect-tolerant architectures and models for integrated circuit defects, faults, and yield. Progress in this area was slowed down by the proprietary nature of yield-related data, and by the lack of appropriate forums for disseminating such information. The goal of this workshop was therefore to provide a forum for a dialogue and exchange of views. A follow-up workshop in October 1989, with C. H. Stapper from IBM and V. K. Jain from the University of South Florida as general co-chairmen, is being organized.
Categories: Computers

High Level Synthesis of ASICs under Timing and Synchronization Constraints

High Level Synthesis of ASICs under Timing and Synchronization Constraints

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECTURE AND DIGITAL SIGNAL ... P. Duzy ISBN: 0-7923–91.99–3 Fault Covering Problems in Reconfigurable VLSI Systems, R. Libeskind-Hadas, N. Hasan, ...

Author: David C. Ku

Publisher: Springer Science & Business Media

ISBN: 9781475721171

Category: Technology & Engineering

Page: 294

View: 652

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.
Categories: Technology & Engineering

The SECD Microprocessor

The SECD Microprocessor

... J. E. Kardontchik ISBN: 0-7923-9195-0 The Synthesis Approach to Digital System Design, P. Michel, U. Lauther, P. Duzy ISBN: 0-7923-9199-3 Fault Covering Problems in Reconfigurable VLSI Systems, R.Libeskind-Hadas, N. Hassan, J. Cong, ...

Author: Brian T. Graham

Publisher: Springer Science & Business Media

ISBN: 9781461535768

Category: Technology & Engineering

Page: 176

View: 371

This is a milestone in machine-assisted microprocessor verification. Gordon [20] and Hunt [32] led the way with their verifications of sim ple designs, Cohn [12, 13] followed this with the verification of parts of the VIPER microprocessor. This work illustrates how much these, and other, pioneers achieved in developing tractable models, scalable tools, and a robust methodology. A condensed review of previous re search, emphasising the behavioural model underlying this style of verification is followed by a careful, and remarkably readable, ac count of the SECD architecture, its formalisation, and a report on the organisation and execution of the automated correctness proof in HOL. This monograph reports on Graham's MSc project, demonstrat ing that - in the right hands - the tools and methodology for formal verification can (and therefore should?) now be applied by someone with little previous expertise in formal methods, to verify a non-trivial microprocessor in a limited timescale. This is not to belittle Graham's achievement; the production of this proof, work ing as Graham did from the previous literature, goes well beyond a typical MSc project. The achievement is that, with this exposition to hand, an engineer tackling the verification of similar microprocessor designs will have a clear view of the milestones that must be passed on the way, and of the methods to be applied to achieve them.
Categories: Technology & Engineering

Field Programmable Gate Arrays

Field Programmable Gate Arrays

... J. E. Kardontchik ISBN: 0-7923-919.5-0 The Synthesis Approach to Digital System Design, P. Michel, U. Lauther, P. Duzy ISBN: 0-7923-919.9-3 Fault Covering Problems in Reconfigurable VLSI Systems, R.Libeskind-Hadas, N. Hassan, ...

Author: Stephen D. Brown

Publisher: Springer Science & Business Media

ISBN: 9781461535720

Category: Computers

Page: 206

View: 963

Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by mask-programmed gate arrays. FPGAs offer an affordable solution for customized VLSI, over a wide variety of applications, and have also opened up new possibilities in designing reconfigurable digital systems. Field-Programmable Gate Arrays discusses the most important aspects of FPGAs in a textbook manner. It provides the reader with a focused view of the key issues, using a consistent notation and style of presentation. It provides detailed descriptions of commercially available FPGAs and an in-depth treatment of the FPGA architecture and CAD issues that are the subjects of current research. The material presented is of interest to a variety of readers, including those who are not familiar with FPGA technology, but wish to be introduced to it, as well as those who already have an understanding of FPGAs, but who are interested in learning about the research directions that are of current interest.
Categories: Computers

Electronic CAD Frameworks

Electronic CAD Frameworks

... J. E. Kardontchik ISBN: 0-7923-919.5-0 The Synthesis Approach to Digital System Design, P. Michel, U. Lauther, P. Duzy ISBN: 0-7923-919.9-3 Fault Covering Problems in Reconfigurable VLSI Systems, R.Libeskind-Hadas, N. Hassan, ...

Author: Timothy J. Barnes

Publisher: Springer Science & Business Media

ISBN: 9781461535584

Category: Technology & Engineering

Page: 195

View: 276

When it comes to frameworks, the familiar story of the elephant and the six blind philosophers seems to apply. As each philoso pher encountered a separate part of the elephant, each pronounced his considered, but flawed judgement. One blind philosopher felt a leg and thought it a tree. Another felt the tail and thought he held a rope. Another felt the elephant's flank and thought he stood before a wall. We're supposed to learn about snap judgements from this alle gory, but its author might well have been describing design automation frameworks. For in the reality of today's product development requirements, a framework must be many things to many people. xiv CAD Frameworks: Integration Technology for CAD As the authors of this book note, framework design is an optimi zation problem. Somehow, it has to be both a superior rope for one and a tremendous tree for another. Somehow it needs to provide a standard environment for exploiting the full potential of computer-aided engineering tools. And, somehow, it has to make real such abstractions as interoperability and interchangeability. For years, we've talked about a framework as something that provides application-oriented services, just as an operating system provides system-level support. And for years, that simple statement has hid the tremendous complexity of actually providing those services.
Categories: Technology & Engineering

Hot Carrier Reliability of MOS VLSI Circuits

Hot Carrier Reliability of MOS VLSI Circuits

... Editor Jonathan Allen Latest Titles The Synthesis Approach to Digital System Design, P. Michel, U. Lauther, P. Duzy ISBN: 0-7923-919.9-3 Fault Covering Problems in Reconfigurable VLSI Systems, R.Libeskind-Hadas, N. Hassan, J. Cong, ...

Author: Yusuf Leblebici

Publisher: Springer Science & Business Media

ISBN: 9781461532507

Category: Technology & Engineering

Page: 212

View: 435

As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
Categories: Technology & Engineering