Memory Management for Synthesis of DSP Software

Memory Management for Synthesis of DSP Software

This book systematically reviews research conducted by the authors on memory minimization techniques for compiling synchronous dataflow (SDF) specifications.

Author: Praveen K. Murthy

Publisher: CRC Press

ISBN: 9781420019476

Category: Technology & Engineering

Page: 320

View: 509

Although programming in memory-restricted environments is never easy, this holds especially true for digital signal processing (DSP). The data-rich, computation-intensive nature of DSP makes memory management a chief and challenging concern for designers. Memory Management for Synthesis of DSP Software focuses on minimizing memory requirements during the synthesis of DSP software from dataflow representations. Dataflow representations are used in many popular DSP design tools, and the methods of this book can be applied in that context, as well as other contexts where dataflow is used. This book systematically reviews research conducted by the authors on memory minimization techniques for compiling synchronous dataflow (SDF) specifications. Beginning with an overview of the foundations of software synthesis techniques from SDF descriptions, it examines aggressive buffer-sharing techniques that take advantage of specific and quantifiable tradeoffs between code size and buffer size to achieve high levels of buffer memory optimization. The authors outline coarse-level strategies using lifetime analysis and dynamic storage allocation (DSA) for efficient buffer sharing as one approach and demonstrate the role of the CBP (consumed-before-produced) parameter at a finer level using a merging framework for buffer sharing. They present two powerful algorithms for combining these sharing techniques and then introduce techniques that are not restricted to the single appearance scheduling space of the other techniques. Extensively illustrated to clarify the mathematical concepts, Memory Management for Synthesis of DSP Software presents a comprehensive survey of state-of-the-art research in DSP software synthesis.
Categories: Technology & Engineering

Software and Compilers for Embedded Systems

Software and Compilers for Embedded Systems

Heterogeneous Memory Management for Embedded Systems. ... Software synthesis and code generation for DSP. IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, 47(9):849-875, September 2000.

Author: Andreas Krall

Publisher: Springer

ISBN: 9783540399209

Category: Computers

Page: 406

View: 233

This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24–26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand pro?t from the assembly of international experts in the ?eld. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in ?elds of interest led to a change of name, and this is when the present name was used for the ?rst time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop.
Categories: Computers

High Level Synthesis for Real Time Digital Signal Processing

High Level Synthesis for Real Time Digital Signal Processing

Register assignment techniques to minimise the number of storage locations, based on the lifetime of scalars, originate from the software compiler technology. In [Aho?7) and [Gol&0], the memory is modelled as a lifetime constraint graph ...

Author: Jan Vanhoof

Publisher: Springer Science & Business Media

ISBN: 9781475722222

Category: Technology & Engineering

Page: 302

View: 805

High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for a low production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.
Categories: Technology & Engineering

Custom Memory Management Methodology

Custom Memory Management Methodology

[211] B.Kim, T. Barnwell III, “Resource allocation and code generation for pointerbased pipelined DSP multiprocessors”, Proc. ... [214] D.Kolson, A.Nicolau, N.Dutt, “Minimization of memory traffic in high-level synthesis”, Proc.

Author: Francky Catthoor

Publisher: Springer Science & Business Media

ISBN: 9781475728491

Category: Computers

Page: 344

View: 997

The main intention of this book is to give an impression of the state-of-the-art in system-level memory management (data transfer and storage) related issues for complex data-dominated real-time signal and data processing applications. The material is based on research at IMEC in this area in the period 1989- 1997. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style and a systematic methodology to make the exploration and optimization of such systems feasible. Our approach is also very heavily application driven which is illustrated by several realistic demonstrators, partly used as red-thread examples in the book. Moreover, the book addresses only the steps above the traditional high-level synthesis (scheduling and allocation) or compilation (traditional or ILP oriented) tasks. The latter are mainly focussed on scalar or scalar stream operations and data where the internal structure of the complex data types is not exploited, in contrast to the approaches discussed here. The proposed methodologies are largely independent of the level of programmability in the data-path and controller so they are valuable for the realisation of both hardware and software systems. Our target domain consists of signal and data processing systems which deal with large amounts of data.
Categories: Computers

Digital Signal Processing for Multimedia Systems

Digital Signal Processing for Multimedia Systems

[1] I. Verbauwhede, F. Catthoor, J. Vandewalle, H. De Man, “Background memory management for the synthesis of algebraic algorithms on multi-processor DSP chips”, Proc. VLSI'89, Int. Conf. on VLSI, Munich, Germany, pp. 209-218, Aug.

Author: Keshab K. Parhi

Publisher: CRC Press

ISBN: 9781351830607

Category: Technology & Engineering

Page: 880

View: 193

Addresses a wide selection of multimedia applications, programmable and custom architectures for the implementations of multimedia systems, and arithmetic architectures and design methodologies. The book covers recent applications of digital signal processing algorithms in multimedia, presents high-speed and low-priority binary and finite field arithmetic architectures, details VHDL-based implementation approaches, and more.
Categories: Technology & Engineering

Hardware Software Co Design

Hardware Software Co Design

Cathedral III: Architecture driven high-level synthesis for high throughput DSP applications. In Proceedings of the 28th ACM/IEEE ... Automating high-level control flow transformations for DSP memory management. In K. Yao, R. Jain, ...

Author: Giovanni DeMicheli

Publisher: Springer Science & Business Media

ISBN: 9789400901872

Category: Computers

Page: 480

View: 569

Concurrent design, or co-design of hardware and software is extremely important for meeting design goals, such as high performance, that are the key to commercial competitiveness. Hardware/Software Co-Design covers many aspects of the subject, including methods and examples for designing: (1) general purpose and embedded computing systems based on instruction set processors; (2) telecommunication systems using general purpose digital signal processors as well as application specific instruction set processors; (3) embedded control systems and applications to automotive electronics. The book also surveys the areas of emulation and prototyping systems with field programmable gate array technologies, hardware/software synthesis and verification, and industrial design trends. Most contributions emphasize the design methodology, the requirements and state of the art of computer aided co-design tools, together with current design examples.
Categories: Computers

High Performance Computing HiPC 2000

High Performance Computing   HiPC 2000

I.Verbauwhede, F.Catthoor, J.Vandewalle, H.De Man, “Background memory management for the synthesis of algebraic algorithms on multi-processor DSP chips”, Proc. VLSI'89, Int. Conf. on VLSI, Munich, Germany, pp. 2098–2118, Aug. 1989. 3.

Author: Mateo Valero

Publisher: Springer

ISBN: 9783540444671

Category: Computers

Page: 574

View: 366

This book constitutes the refereed proceedings of the 7th International Conference on High Performance Computing, HiPC 2000, held in Bangalore, India in December 2000. The 46 revised papers presented together with five invited contributions were carefully reviewed and selected from a total of 127 submissions. The papers are organized in topical sections on system software, algorithms, high-performance middleware, applications, cluster computing, architecture, applied parallel processing, networks, wireless and mobile communication systems, and large scale data mining.
Categories: Computers

Modeling Verification and Exploration of Task Level Concurrency in Real Time Embedded Systems

Modeling  Verification and Exploration of Task Level Concurrency in Real Time Embedded Systems

Foreground memory management in data path synthesis. ... Mwave/OS: A predicatable real-time DSP operating system. ... Classification of Fixed-Point DSP Cores in relation to Program Flow Management and Exception Handling.

Author: Filip Thoen

Publisher: Springer Science & Business Media

ISBN: 9781461544371

Category: Computers

Page: 438

View: 800

system is a complex object containing a significant percentage of elec A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge neous and contain almost always programmable components.
Categories: Computers

Readings in Hardware software Co design

Readings in Hardware software Co design

D. Kirovski, C. Lee, M. Potkonjak, and W. H. Mangione-Smith, “Application-driven synthesis of memory-intensive ... eflects during co-synthesis. at C. H. Gebotys, A minimum-cost circulation approach to DSP address-code generation,” IEEE ...

Author: Giovanni De Micheli

Publisher: Morgan Kaufmann

ISBN: 9781558607026

Category: Computers

Page: 697

View: 450

This title serves as an introduction ans reference for the field, with the papers that have shaped the hardware/software co-design since its inception in the early 90s.
Categories: Computers

Software Synthesis from Dataflow Graphs

Software Synthesis from Dataflow Graphs

[Bhat')4a] S. S. Bhattacharyya and E. A. Lee, “Memory management for dataflow programming of multirate signal ... “Optimal Parenthesization of Lexical Orderings for DSP Block Diagrams,” IEEE Workshop on VLSI Signal Processing, Osaka, ...

Author: Shuvra S. Bhattacharyya

Publisher: Springer Science & Business Media

ISBN: 9781461313892

Category: Technology & Engineering

Page: 190

View: 116

Software Synthesis from Dataflow Graphs addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys® (both commercial tools), and the Ptolemy environment from the University of California at Berkeley. A key property of the SDF model is that static schedules can be determined at compile time. This removes the overhead of dynamic scheduling and is thus useful for real-time DSP programs where throughput requirements are often severe. Another constraint that programmable DSPs for embedded systems have is the limited amount of on-chip memory. Off-chip memory is not only expensive but is also slower and increases the power consumption of the system; hence, it is imperative that programs fit in the on-chip memory whenever possible. Software Synthesis from Dataflow Graphs reviews the state-of-the-art in constructing static, memory-optimal schedules for programs expressed as SDF graphs. Code size reduction is obtained by the careful organization of loops in the target code. Data buffering is optimized by constructing the loop hierarchy in provably optimal ways for many classes of SDF graphs. The central result is a uniprocessor scheduling framework that provably synthesizes the most compact looping structures, called single appearance schedules, for a certain class of SDF graphs. In addition, algorithms and heuristics are presented that generate single appearance schedules optimized for data buffering usage. Numerous practical examples and extensive experimental data are provided to illustrate the efficacy of these techniques.
Categories: Technology & Engineering

Light Propagation in Periodic Media

Light Propagation in Periodic Media

REFERENCES [ 1 ] I. Verbauwhede , F. Catthoor , J. Vandewalle , H. De Man , “ Background memory management for the synthesis of algebraic algorithms on multi - processor DSP chips " , Proc . VLSI'89 , Int . Conf . on VLSI , Munich ...

Author: Michel Neviere

Publisher: CRC Press

ISBN: 9781482275919

Category: Science

Page: 432

View: 899

Based on more than 30 years of research on differential theories of gratings, this book describes developments in differential theory for applications in spectroscopy, acoustics, X-ray instrumentation, optical communication, information processing, photolithography, high-power lasers, high-precision engineering, and astronomy. Introducing the Fast Fourier Factorization approach to improve the convergence of a truncated series, the book examines multilayers, stacked gratings, crossed gratings, photonic crystals, and isotropic and anisotropic materials; techniques and examples in grating design; and Maxwell equations in a truncated Fourier space.
Categories: Science

Data Access and Storage Management for Embedded Programmable Processors

Data Access and Storage Management for Embedded Programmable Processors

[494] ..., "Synopsys Digital Signal Processing - COSSAP Home Page”, http://www.synopsys.com/products/dsp/dsp.html [495] ... [496] O.Temam, “An algorithm for optimally exploiting spatial and temporal locality in upper memory levels”, ...

Author: Francky Catthoor

Publisher: Springer Science & Business Media

ISBN: 9781475749038

Category: Computers

Page: 306

View: 185

Data Access and Storage Management for Embedded Programmable Processors gives an overview of the state-of-the-art in system-level data access and storage management for embedded programmable processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are data-dominated in the sense that their cost related aspects, namely power consumption and footprint are heavily influenced (if not dominated) by the data access and storage aspects. The material is mainly based on research at IMEC in this area in the period 1996-2001. In order to deal with the stringent timing requirements and the data dominated characteristics of this domain, we have adopted a target architecture style that is compatible with modern embedded processors, and we have developed a systematic step-wise methodology to make the exploration and optimization of such applications feasible in a source-to-source precompilation approach.
Categories: Computers

Designing Embedded Processors

Designing Embedded Processors

Catthoor, F., DeGreef, E., and Suytack, S. (1998) Custom Memory Management Methodology: Exploration of Memory ... C., Park, I., Hwang, S., and Kyung, C. (1999a) Synthesis of Application Specific Instructions for Embedded DSP Software.

Author: Jörg Henkel

Publisher: Springer Science & Business Media

ISBN: 9781402058691

Category: Technology & Engineering

Page: 550

View: 353

To the hard-pressed systems designer this book will come as a godsend. It is a hands-on guide to the many ways in which processor-based systems are designed to allow low power devices. Covering a huge range of topics, and co-authored by some of the field’s top practitioners, the book provides a good starting point for engineers in the area, and to research students embarking upon work on embedded systems and architectures.
Categories: Technology & Engineering

System on Chip for Real Time Applications

System on Chip for Real Time Applications

On the other hand, embedded systems cannot use software run-time memory management since it is expensive in ... Chinook [20] and Polis [21] and data flow dominated methodologies such as COSSAP (Commercial DSP synthesis tool from ...

Author: Wael Badawy

Publisher: Springer Science & Business Media

ISBN: 9781461503514

Category: Technology & Engineering

Page: 456

View: 276

System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application. It will also be useful to graduate and undergraduate students in electrical and computer engineering and computer science. A selected set of papers from the 2nd International Workshop on Real-Time Applications were used to form the basis of this book. It is organized into the following chapters: -Introduction; -Design Reuse; -Modeling; -Architecture; -Design Techniques; -Memory; -Circuits; -Low Power; -Interconnect and Technology; -MEMS. System-on-Chip for Real-Time Applications contains many signal processing applications and will be of particular interest to those working in that community.
Categories: Technology & Engineering

Low Power CMOS Design

Low Power CMOS Design

M. Moonen , “ Memory and data - path mapping for image and video appliFigure 10 gives an overview of the relative power ... and overmemory management for the synthesis of algebraic algorithms on multiprocessor DSP chips , ” Proc .

Author: Anantha Chandrakasan

Publisher: John Wiley & Sons

ISBN: 9780780334298

Category: Technology & Engineering

Page: 656

View: 302

This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.
Categories: Technology & Engineering

Energy Efficient Hardware Software Co Synthesis Using Reconfigurable Hardware

Energy Efficient Hardware Software Co Synthesis Using Reconfigurable Hardware

They are used in many application areas, ranging from wireless baseband digital signal processing to embedded processing ... Embedded processing applications may need more dedicated memory blocks to store and cache the software programs ...

Author: Jingzhao Ou

Publisher: CRC Press

ISBN: 1584887427

Category: Technology & Engineering

Page: 224

View: 599

Rapid energy estimation for energy efficient applications using field-programmable gate arrays (FPGAs) remains a challenging research topic. Energy dissipation and efficiency have prevented the widespread use of FPGA devices in embedded systems, where energy efficiency is a key performance metric. Helping overcome these challenges, Energy Efficient Hardware-Software Co-Synthesis Using Reconfigurable Hardware offers solutions for the development of energy efficient applications using FPGAs. The book integrates various high-level abstractions for describing hardware and software platforms into a single, consistent application development framework, enabling users to construct, simulate, and debug systems. Based on these high-level concepts, it proposes an energy performance modeling technique to capture the energy dissipation behavior of both the reconfigurable hardware platform and the target applications running on it. The authors also present a dynamic programming-based algorithm to optimize the energy performance of an application running on a reconfigurable hardware platform. They then discuss an instruction-level energy estimation technique and a domain-specific modeling technique to provide rapid and fairly accurate energy estimation for hardware-software co-designs using reconfigurable hardware. The text concludes with example designs and illustrative examples that show how the proposed co-synthesis techniques lead to a significant amount of energy reduction. This book explores the advantages of using reconfigurable hardware for application development and looks ahead to future research directions in the field. It outlines the range of aspects and steps that lead to an energy efficient hardware-software application synthesis using FPGAs.
Categories: Technology & Engineering

Software Engineering

Software Engineering

ALU ASIC Callback CE Channel CISC CLA CPI CS CSA CSP Cycle DCache Descriptor DMA DSP EDA EE FIFO FPGA FPU FW HandelC ... Usually used for large page sizes, in R16 it is used for 32-byte lines leading onto object memory management.

Author: Krzysztof Zieliński

Publisher: IOS Press

ISBN: 9781586035594

Category: Computers

Page: 431

View: 187

The capability to design quality software and implement modern information systems is at the core of economic growth in the 21st century. This book aims to review and analyze software engineering technologies, focusing on the evolution of design and implementation platforms as well as on novel computer systems.
Categories: Computers

Programmable Digital Signal Processors

Programmable Digital Signal Processors

8 Hardware / Software Cosynthesis of DSP Systems Shuvra S. Bhattacharyya University of Maryland at College Park ... that are not covered here include memory management ( 1-5 ) , which is discussed in Chapter 9 ; DSP code generation from ...

Author: Yu Hen Hu

Publisher: CRC Press

ISBN: 0203908066

Category: Technology & Engineering

Page: 456

View: 198

"Presents the latest developments in the prgramming and design of programmable digital signal processors (PDSPs) with very-long-instruction word (VLIW) architecture, algorithm formulation and implementation, and modern applications for multimedia processing, communications, and industrial control."
Categories: Technology & Engineering

VLSI Synthesis of DSP Kernels

VLSI Synthesis of DSP Kernels

... Sharad Malik, “Memory Bank and Register Allocation in Software Synthesis for ASIPs", IEEE International Conference on CAD, ICCAD1995, pp. 388-392 Earl Swartzlander Jr., VLSI Signal Processing Systems, Kluwer Academic Publishers, ...

Author: Mahesh Mehendale

Publisher: Springer Science & Business Media

ISBN: 9781475733556

Category: Technology & Engineering

Page: 210

View: 338

A critical step in the design of a DSP system is to identify for each of its components an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. This essential book covers architectures that offer varying degrees of programmability.
Categories: Technology & Engineering

High Performance Computing

High Performance Computing

I. Verbauwhede , F.Catthoor , J.Vandewalle , H.De Man , " Background memory management for the synthesis of algebraic algorithms on multi - processor DSP chips " , Proc . VLSI'89 , Int . Conf . on VLSI , Munich , Germany , pp .

Author:

Publisher:

ISBN: UOM:39015049108197

Category: High performance computing

Page:

View: 293

Categories: High performance computing